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PRELIMINARY
CY62135V MoBLTM CY62135V18 MoBL2TM
128K x 16 Flash Compatible Static RAM
Features
* Low voltage range: -- CY62135V: 2.7V-3.3V -- CY62135V18: 1.65-1.95V * Ultra-low active/standby power * Easy memory expansion with CE /CE2 and OE features * Automatic power-down when deselected * Pin out compatible with standard Flash devices * Shipped in Wafer/Die form BHE are HIGH [1]. The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE HIGH or CE2 LOW), outputs are disabled (OE HIGH), BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, CE2 HIGH and WE LOW). Writing to the device is accomplished by taking chip enable (CE) LOW, CE2 HIGH, and write enable (WE) inputs LOW. If byte low enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O 7), is written into the location specified on the address pins (A0 through A16). If byte high enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by taking chip enable (CE) LOW, CE2 HIGH, and output enable (OE) LOW while forcing the write enable (WE) HIGH. If byte low enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If byte high enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the Truth Table at the back of this data sheet for a complete description of read and write modes. The CY62135V/CY62135V18 are shipped in a wafer form.
Functional Description
The CY62135V and CY62135V18 are high-performance CMOS static RAMs organized as 128K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery LifeTM (MoBLTM) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not toggling. The device can also be put into standby mode when deselected (CE HIGH or CE2 LOW) or when CE is LOW and when CE2 is HIGH and both BLE and
Logic Block Diagram
DATA IN DRIVERS A9 A8 A7 A6 A3 A2 A1 A0
ROW DECODER
128K x 16 RAM Array 1024 X 2048
SENSE AMPS
I/O0-I/O7 I/O8-I/O15
COLUMN DECODER
A10 A11 A12 A13 A14 A15 A16
BHE WE OE BLE CE
Power-Down Circuit
BHE BLE
CE2
Note: 1. Tying BBDISB to VCC will disable the Byte Enable Power Down Feature. Tying it to VSS will enable the Byte Enable Power Down Feature. More Battery Life and MoBL are trademarks of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134
* 408-943-2600 December 21, 1999
PRELIMINARY
Wafer and Die Specifications
Mechanical Specifications Process/Technology Wafer Diameter Wafer Thickness, background Backside Wafer Surface Bond Pad Specifications Bond Pad Opening Topside Passivation Bond Pad Metal Composition Bond Pad Locations
CY62135V MoBLTM CY62135V18 MoBL2TM
CMOS, Double Metal, 0.25 203.2 mm 355.6 m Silicon
80 TBD 300 A Al, 0.5% Cu
The next figure shows the locations of the bond pads and table below provides the X and Y coordinates of these bond pads.
A15 A14 A13 A12 A16 VSSQ D15 D7 A11 A10 A9 A8 VCC CE2 WE VSS A15 BHE BLE A17 A7 A6 A5 A4 A3 A2 A1 PTM D14 D6 D13 D5 D12 D4 BBDISB VCCQ VCC D11 D3 D10 D2 D9 D1 D8 D0 OE VSS CE A0
PAD Locations on Die (Die Size: 3.498 mm x 5.731 mm)
2
PRELIMINARY
Pin Definitions
Pin Name A15 A14 A13 A12 A11 A10 A9 A8 VCC CE2 WEB VSS BHE BLE NC A7 A6 A5 A4 A3 A2 A1 A0 CE VSS OE D0 D8 D1 D9 D2 D10 D3 D11 VCC VCCQ BBDISB D4 D12 D5 D13 D6 D14 D7 D15 VSSQ A16 PTM Location -1635.3 -1635.300 -1635.300 -1635.300 -1635.300 -1635.300 -1635.300 -1635.300 -1635.300 -1635.300 -1635.300 -1635.300 -1635.300 -1635.300 -1635.300 -1635.300 -1635.300 -1635.300 -1635.300 -1635.300 -1635.300 -1635.300 1618.575 1618.575 1618.575 1618.575 1618.575 1618.575 1618.575 1618.575 1618.575 1618.575 1618.575 1618.575 1618.575 1618.575 1618.575 1618.575 1618.575 1618.575 1618.575 1618.575 1618.575 1618.575 1618.575 1618.575 1618.575 -1635.300
CY62135V MoBLTM CY62135V18 MoBL2TM
Location Function 1944.925 Address 1805.25 Address 1633.7 Address 1494.025 Address 1102.475 Address 962.8 Address 791.275 Address 651.575 Address 514.275 Power 376.975 Active HIGH Chip Enable 237.275 Active LOW Write Enable -186.65 Ground -323.95 Active LOW Byte High Enable -463.625 Active LOW Byte Low Enable -635.175 Address Expansion for 4M -774.85 Address -946.4 Address -1086.075 Address -1477.625 Address -1617.3 Address -1788.85 Address -1928.525 Address -2099.425 Address -1959.725 Active LOW Chip Enable -1821.525 Ground -1700.45 Active LOW Output Enable -1528.925 I/O Data Bus -1348.475 I/O Data Bus -1147.25 I/O Data Bus -966.8 I/O Data Bus -795.25 I/O Data Bus -614.8 I/O Data Bus -413.575 I/O Data Bus -233.125 I/O Data Bus -95.825 Power 251.375 Power for I/O Pins 389.6 Byte Enable Power Down Disable[1] 533.65 I/O Data Bus 714.1 I/O Data Bus 915.325 I/O Data Bus 1095.775 I/O Data Bus 1267.3 I/O Data Bus 1447.75 I/O Data Bus 1648.975 I/O Data Bus 1829.425 I/O Data Bus 1970.675 Ground for I/O Pins 2091.925 Address -2295.050 Parallel Test Mode Pad, internally held low with a resistor, meant for testing purposes only.
3
PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied .................................................. -55C to +125C Supply Voltage to Ground Potential ............... -0.5V to +4.6V
CY62135V MoBLTM CY62135V18 MoBL2TM
DC Voltage Applied to Outputs in High Z State[2] ................................... -0.5V to VCC + 0.5V DC Input Voltage[2] ................................ -0.5V to VCC + 0.5V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current .................................................... >200 mA
Operating Range
Device CY62135V CY62135V18 Industrial Industrial Range Ambient Temperature -40C to +85C -40C to +85C VCC 2.7V to 3.3V 1.65V to 1.95V
Shaded areas contain advance information.
Product Portfolio
Power Dissipation (Commercial) VCC Range Product CY62135V CY62135V18 VCC(min) 2.7V 1.65V VCC(typ)[3] 3.0V 1.8V VCC(max) 3.3V 1.95V Speed 70 ns 70 ns Operating (ICC) Typ.[3] 7 3 Maximum 12 mA 7 mA Typ.[3] 1 A 1 A Standby (ISB2) Maximum 10 A 15 A
Shaded areas contain advance information.
Electrical Characteristics Over the Operating Range
CY62135V Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current VCC Operating Supply Current GND < VI < VCC GND < VO < VCC, Output Disabled IOUT = 0 mA, f = fMAX = 1/tRC, CMOS levels CE > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V, f = fMAX CE > VCC - 0.3V VIN > VCC - 0.3V or VIN < 0.3V, f = 0 1 VCC = 3.3V Test Conditions IOH = -1.0 mA IOL = 2.1 mA VCC = 2.7V VCC = 2.7V VCC = 3.3V VCC = 2.7V 2.2 -0.5 -1 -1 +1 +1 7 Min. 2.4 0.4 VCC + 0.5V 0.8 +1 +1 12 Typ.[3] Max. Unit V V V V A A mA
IOUT = 0 mA, f = 1 MHz, CMOS Levels ISB1 Automatic CE Power-Down Current-- CMOS Inputs Automatic CE Power-Down Current-- CMOS Inputs
1
2 100
mA A
ISB2
10
A
Notes: 2. VIL (min) = -2.0V for pulse durations less than 20 ns. 3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC Typ, TA = 25C.
4
PRELIMINARY
Electrical Characteristics Over the Operating Range
CY62135V MoBLTM CY62135V18 MoBL2TM
CY62135V18 Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current VCC Operating Supply Current GND < VI < VCC GND < VO < VCC, Output Disabled IOUT = 0 mA, f = fMAX = 1/tRC, CMOS levels CE > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V, f = fMAX CE > VCC - 0.3V VIN > VCC - 0.3V or VIN < 0.3V, f = 0 1 VCC = 1.95V Test Conditions IOH = -0.1 mA IOL = 0.1 mA VCC = 1.65V VCC = 1.65V VCC = 1.95V VCC = 1.65V 1.4 -0.5 -1 -1 +1 +1 3 Min. 1.5 0.2 VCC + 0.3V 0.4 +1 +1 7 Typ.[3] Max. Unit V V V V A A mA
IOUT = 0 mA, f = 1 MHz, CMOS Levels ISB1 Automatic CE Power-Down Current-- CMOS Inputs Automatic CE Power-Down Current-- CMOS Inputs
1
2 100
mA A
ISB2
15
A
Capacitance[4]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.0V Max. 6 8 Unit pF pF
Note: 4. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
R1 VCC OUTPUT 30 pF INCLUDING JIG AND SCOPE Equivalent to: THEVENIN EQUIVALENT RTH OUTPUT V R2 VCC Typ 10% GND < 5 ns ALL INPUT PULSES 90% 90% 10% < 5 ns
Parameters R1 R2 RTH VTH Shaded area contain advanced information.
3.0V 1105 1550 645 1.75
1.8V 15294 11300 6500 0.85
UNIT Ohms Ohms Ohms Volts
5
PRELIMINARY
Data Retention Characteristics (Over the Operating Range)
Parameter VDR VDR ICCDR Description VCC for Data Retention (CY62135V18) VCC for Data Retention (CY62135V) Data Retention Current VCC = 1.0V CE > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V No input may exceed VCC+0.3V 0 tRC Conditions[5] Min. 1.0 1.0
CY62135V MoBLTM CY62135V18 MoBL2TM
Typ.[3]
Max. 1.95 3.3
Unit V V A
0.1
1
tCDR[4] tR
Chip Deselect to Data Retention Time Operation Recovery Time
ns ns
Data Retention Waveform
DATA RETENTION MODE VCC
VCC(min)
tCDR
VDR > 1.0 V
VCC(min)
tR
CE
Note: 5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to VCC typ., and output loading of the specified IOL/IOH and 30-pF load capacitance.
6
PRELIMINARY
Switching Characteristics Over the Operating Range[5]
CY62135V MoBLTM CY62135V18 MoBL2TM
70 ns Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE WRITE CYCLE tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE
[8, 9]
Description Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z[6] OE HIGH to High Z CE LOW to Low Z CE HIGH to High Z
[6, 7] [6] [6, 7]
Min. 70
Max.
Unit ns
70 0 70 35 5 25 10 25 0 70 70 10 25 70 60 60 0 0 50 30 0 25 10
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
CE LOW to Power-Up CE HIGH to Power-Down BHE / BLE LOW to Data Valid BHE / BLE LOW to Low Z BHE / BLE HIGH to High Z Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE LOW to High Z
[6, 7] [6]
WE HIGH to Low Z
Switching Waveforms
Read Cycle No. 1 [10,11]
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Notes: 6. At any given temperature and voltage condition, t HZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 9. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 10. Device is continuously selected. OE, CE = VIL, CE2 = VIH . 11. WE is HIGH for read cycle.
7
PRELIMINARY
Switching Waveforms (continued)
Read Cycle No. 2 [11, 12, 13]
CCE tACE OE tDOE BHE/BLE tLZOE tRC
CY62135V MoBLTM CY62135V18 MoBL2TM
tPD tHZCE
tHZOE
t HZBE tDBE tLZBE DATA OUT HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% 50% ISB ICC DATA VALID HIGH IMPEDANCE
[8, 12, 14, 15]
Write Cycle No. 1 (WE Controlled)
tWC ADDRESS
CCE tAW WE tSA tPWE tHA
BHE/BLE
tBW
OE tSD DATA I/O NOTE 16 tHZOE
Notes: 12. CCE is the combination of both CE and CE2(CE = VIL, CE2 = VIH ). 13. Address valid prior to or coincident with CE transition LOW. 14. Data I/O is high impedance if OE = VIH. 15. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 16. During this period, the I/Os are in output state and input signals should not be applied.
tHD
DATAIN VALID
8
PRELIMINARY
Switching Waveforms (continued)
Write Cycle No. 2 (CE Controlled)
[8, 12, 14, 15]
CY62135V MoBLTM CY62135V18 MoBL2TM
tWC ADDRESS CCE tSA tAW tHA tSCE
BHE/BLE
tBW
WE
tPWE tSD tHD
DATA I/O
DATAIN VALID
Write Cycle No. 3 (WE Controlled, OE LOW)
[9, 12, 15]
tWC ADDRESS
CCE tAW tBW tSA tHA
BHE/BLE WE
tSD DATA I/O NOTE 16 tHZWE DATAIN VALID
tHD
tLZWE
9
PRELIMINARY
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4 1.2 NORMALIZED ICC NORMALIZED ICC 1.0 0.8 0.6 0.4 0.2 0.0 1.7 2.2 2.7 3.2 3.7 0.10 1 5 10 15 VIN =VCC typ. TA =25C I CC 1.00 VCC =3.3V TA =25C 1.50 NORMALIZED I CC vs. CYCLE TIME
CY62135V MoBLTM CY62135V18 MoBL2TM
STANDBY CURRENT vs. AMBIENT TEMPERATURE 3.0 2.5 2.0 ISB2 A 1.5 1.0 0.5 0.0 -0.5 VCC =VCC typ. VIN =VCC typ.
ISB
0.50
-55
25
105
SUPPLY VOLTAGE (V)
CYCLE FREQUENCY (MHz)
AMBIENT TEMPERATURE (C)
Truth Table
CE H X X L L L L L L L L L CE2 X L X H H H H H H H H H WE X X X H H H H H H L L L OE X X X L L L H H H X X X BHE X X H L H L L H L L H L BLE X X H L L H L L H L L H High Z High Z High Z
[1]
Inputs/Outputs
Mode Deselect/Power-Down Deselect/Power-Down Deselect/Power-Down [1] Read Read Read Deselect/Output Disabled Deselect/Output Disabled Deselect/Output Disabled Write Write Write
Data Out (I/O O-I/O 15) Data Out (I/O O-I/O 7); I/O8-I/O15 in High Z Data Out (I/O 8-I/O15); I/O0 -I/O 7 in High Z High Z High Z High Z Data In (I/O O-I/O 15) Data In (I/O O-I/O 7); I/O8-I/O15 in High Z Data In (I/O 8-I/O15); I/O0-I/O7 in High Z
Ordering Information
Speed (ns) 70 70 Ordering Code CY62135V-WAF CY62135V18-WAF Package Name TBD TBD Wafer Boxes Wafer Boxes Package Type Operating Range Industrial Industrial
Shaded areas contain advance information.
Document #: 38-00870
(c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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